Conventionally, there are a great variety of semiconductor packages using leadframes as chip carriers, such as quad flat non-leaded (QFN) semiconductor package. The characteristic feature of this QFN semiconductor package is that, unlike a quad flat package (QFP), it does not have external leads being formed outside the package for electrically connecting with external devices, thereby reducing the dimension of the semiconductor packages. However, with the semiconductor product being striven towards miniaturization continuously, limited by the thickness of an encapsulant, the overall thickness of the conventional leadframe QFN semiconductor package may not be further reduced, therefore the industry has developed a semiconductor package without a chip carrier, which is capable of making overall thickness of the semiconductor package without the chip carrier more light-weight than conventional leadframe QFN semiconductor package.
Referring to FIG. 1, a non-carrier type semiconductor package disclosed by U.S. Pat. No. 5,830,800 is illustrated herein. The semiconductor package is formed by first forming a plurality of pads 12 on a copper carrier (not shown in FIG. 1). Then, a chip 13 is mounted on the copper carrier and electrically connected to the pads 12 via bonding wires 14. After that, an encapsulant 15 is formed by a molding process, and then the copper carrier is removed by etching to expose the pads. Then a solder mask 11 is used to define positions of the pads for implanting solder balls on thereof. In such ways, the semiconductor package without a chip carrier is formed. The related technology is referred in U.S. Pat. Nos. 6,770,959, 6,989,294, 6,933,594 and 6,872,661.
However, the pads 12 have a thickness of about 1 μm to 5 μm, and have a poor bonding with the encapsulant 15, delamination can easily occur between the pads 12 and the encapsulant 15, even causing the break of the bonding wires 14. Furthermore, the manufacturing cost is increased by the use of costly metals such as Au, Pd and the like as an etching resist layer for removing the copper carrier to form the pads 12.
To improve the forgoing problems, a fabrication method is disclosed in U.S. Pat. No. 6,498,099, as shown in FIG. 2A to FIG. 2D′. The method comprises: providing a copper carrier 20, etching a top surface of the copper carrier 20 to form pads 22 as electrical terminals and a die pad 21 for mounting a chip, and plating a plating layer 27 such as Ni or Ag and the like on the top surface of the copper carrier 20; mounting a semiconductor chip 23 on the die pad 21, and connecting the chip 23 to the pads 22 by bonding wires 24, so as to make the bonding wires 24 and the pads 22 effectively bonded, and forming an encapsulant 25 encapsulating the semiconductor chip 23, the bonding wires 24 and the top surface of the copper carrier 20; etching an bottom surface of the copper carrier 20 to expose the encapsulant 25 while remaining the pads 22 and the die pad 21; and forming electroless aurum (Au) plating on the bottom surface of the pads for implanting solder balls 26 to allow the semiconductor package to be solder bonded to a printed circuit carrier (PCB) 28 by solder joints formed by reflowing the solder balls 26.
Unlike U.S. Pat. No. 5,830,800 using Au/Pd as an etching resist layer, the fabrication method uses a nickel (Ni) plating layer or a silver plating layer, and thus reduces the costs. However, there is a poor bonding between the plating layer, such as nickel or silver, and the encapsulant, delamination is caused due to thermal stress, and it further causes moisture penetrating (as shown in FIG. 2C′). Moreover, after the package is solder bonded to the PCB 28, due to the poor bonding between the encapsulant 25 and the silver layer, an incident of the pad 22 dropping off as shown in FIG. 2D′ is happened, so as to cause the package to be invalid. Furthermore, in the fabrication method, die-mounting, wire-bonding and molding processes should be performed on the half etched copper carrier, because the thickness of the copper carrier is reduced a half so as to make the copper carrier be pliable and thus is difficult for transportation during fabricating, and causes the copper carrier to bend because of heat affecting. What is more, when I/O terminals of the electrical terminal are increased, bonding wire cross may easily happen because of the design of the pads 22 arranged in an array, thus causing bonding wire short problem. The correlative reference such as U.S. Pat. No. 6,700,188 also has the same problem.
Therefore, how to provide a semiconductor package without chip carrier and a fabrication method thereof so as to reduce the manufacturing cost, avoid the delimitation problem, produce and transparent easily has become urgent.